If value $XY is written, the transfer will copy $XY00-$XY9F to $FE00-$FE9F. When this register is written to, an OAM DMA transfer starts immediately. $FF45 - LYC: LCD Y compareĪs long as LY has the same value as this register, STAT bit 2 is set. Note that the LCD is in VBlank for part of line 0 see (TODO). Values 0-143 indicate VDraw, values 144-153 indicate VBlank. Indicates which line the LCD is currently processing. Note that on DMG, writing to this register may assert a STAT IRQ refer to STAT writing IRQ. Selecting more than one source may trigger STAT IRQ blocking. 0: Background enable (on CGB: Background & window enable)īits 4–6 select which sources are considered for the STAT interrupt.2: TIMA doesn’t increment when this bit is reset.0–1: Select at which frequency TIMA increases.When TIMA overflows, this register’s contents are copied to it. The way the increment is performed in hardware causes spurious increments under certain conditions, refer to Timer. When it overflows, a Timer IRQ is asserted, and this register is reloaded with TMA’s value. This register is incremented by the CPU clock. See the Super Game Boy section for more information. BitĪdditionally, bits 4 and 5 are used for communicating with the SGB. If neither bit 4 or 5 is selected then all keys read 1. a 0 value implies one or both of the associated keys are pressed). If bits 4 and 5 are both low, then the combination of the D-pad and face buttons is ANDed (i.e. Keys are pulled low (to 0) when pressed and high (to 1) when unpressed.
The hardware multiplexes the D-pad and the face buttons so only four buttons can be read at a time, based on the value of bits 4 and 5 (0 for select, 1 for deselect). This register is used for reading joypad input. This section describes the bit mappings of memory mapped I/O. See CGB-specific memory mapped I/O for additional registers in CGB mode. $FF22 - NR43: Audio channel 4 frequency.$FF20 - NR41: Audio channel 4 sound length.$FF1D - NR33: Audio channel 3 frequency.$FF1B - NR31: Audio channel 3 sound length.$FF18 - NR23: Audio channel 2 frequency.$FF16 - NR21: Audio channel 2 sound length/wave duty.$FF13 - NR13: Audio channel 1 frequency.$FF11 - NR11: Audio channel 1 sound length/wave duty.$FEA0 – $FEFF: Invalid OAM region (behavior varies per revision).$FE00 – $FE9F: Object Attribute Memory (OAM).$E000 – $FDFF: ECHO (WRAM secondary mapping).$A000 – $BFFF: External bus (RAM region).$0000 – $7FFF: External bus (ROM region).T states or T cycles (“transistor”(?) states, 1:1 clock) are the base unit of system operation and many components are clocked directly on T state.M cycles (“machine” cycles, 1:4 clock) are the base unit of CPU instructions.Two types of cycles: T states and M cycles.CGB: optionally clocked at 8.388608 MHz.The Game Boy uses a Sharp SM83, which is similar to Intel 8080, Zilog Z80, and other i8080 knockoffs. 8 object palettes (index 0 is transparent, 3 effective colors per palette).2 object palettes (index 0 is transparent, 3 effective colors per palette).CGB version is optionally clocked at 8.388608 MHz (2x DMG CPU).Similar instruction set to Intel 8080 and Zilog Z80, sometimes erroneously referred to as a Z80 or LR35902.
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